In electronic circuits, metastability refers to the persistence of a non-equilibrium electronic state for an extended period of time (i.e., for longer than a clock cycle). For example, a flip-flop is an electronic device that may suffer from metastability. It has two well-defined stable states, traditionally designated 0 (e.g., 0 to 0.8 volts for TTL) and 1 (e.g., 2.4 to 5 volts for TTL), but under certain conditions it can hover between (e.g., 0.8 to 2.4 volts for TTL) them for longer than a clock cycle.
For example, in a communications network, a digital subscriber line (“DSL”) access multiplexer (“DSLAM”) is a device that serves as a point of interface between a number of subscriber premises and a carrier network. It is a packet multiplexer, serving to multiplex data packets from multiple customers in order to transmit them over one or more high-speed circuits. A hybrid IP/ATM DSLAM supports both Internet Protocol (“IP”) and Asynchronous Transfer Mode (“ATM”) networks. In a hybrid IP/ATM DSLAM, the IP and ATM sides of the DSLAM may be treated as two independent systems each with its own independent asynchronous reset. When one side (e.g., the IP system) of the hybrid DSLAM resets it is often not desirable to require the other side (e.g., the ATM system) to also reset. When a reset of one side of the hybrid DSLAM occurs, all synchronous interfaces between, the two sides of the hybrid DSLAM are subject to a potential meta-stability event. This occurs because when a first system (e.g., the IP system) is reset, traditionally, the reset is applied asynchronously and the interfaces to the system change state asynchronously, thus having the potential to violate set-up or hold times for signals at the far end of the interface coupled to a second system (e.g., the ATM system) which is not being reset. This can lead to a meta-stable event in the second system (e.g., the ATM system) which is not reset, possibly resulting in a finite state machine entering an undefined state from which it can not recover without also being reset. For reference, the expression “set-up time” refers to the time required for the input signal at a flip-flop to be valid before the incoming clock edge arrives. And, the expression “hold time” refers to the time required for the input data signal to remain valid after the clock edge has transitioned.
Note that unlike hybrid IP/ATM DSLAMs, in traditional IP only and ATM only DSLAMs, synchronous interfaces between devices are in the same reset domain and therefore the problem described above does not typically occur. Synchronous interfaces are based on the inherent assumption that set-up and hold times for the interface will never be violated (this is part of the specification for the interface) and therefore steps are generally not taken within a device to ensure that it can tolerate a setup or hold time violation on an external interface.
FIG. 1 is a block diagram illustrating a metastability filtering circuit 100 in accordance with the prior art. To protect against set-up and hold time violations resulting in a metastable event when signals cross clock domains within a device, the prior art circuit 100 pipelines input signals 110 from a first clock domain using multiple registers (e.g., “D”-type flip-flops) 120, 130 clocked by the second clock domain's clock 140. This technique greatly reduces the probability of set-up and/or hold time violations at the output 150 of the last register stage 130 of the circuit 100, thus reducing the probability of a metastable event affecting a register (not shown) following the last stage 130 in the circuit 100. This circuit is typically used for eliminating (or rendering negligible) metastability in cross-clock domain crossings. Pipeline stages of 2 or 3 registers may be implemented with this type of circuit.
However, the above circuit is not effective for protecting against metastability across a synchronous interface between systems in a device that each have separate reset domains, for the following reasons. First, the interface protocol's response time to changes in input control signals (e.g., an enable signal in a Utopia™ interface) arriving at the interface may be such that delaying control signals for multiple clock cycles through pipelining results in an inability to maintain the interface protocol. Second, many off-the-shelf field programmable gate array (“FPGA”) or/application-specific integrated circuit (“ASIC”) cores are pre-designed based on the timing/protocol specific for the type of synchronous interface and therefore cannot accept additional delay in signals received from the interface.
A need therefore exists for an improved metastability filtering circuit for devices having multiple reset domains. Accordingly, a solution that addresses, at least in part, the above and other shortcomings is desired.